Set is tetchy a background pixel is

Set theory is the language of mathematical
morphology. In image processing, morphology
was first used by G.Matheron as a methodology
which analyzes an image based on a predefined
geometric shape by applying set operations on the
image. The image operations of mathematical
morphology, known as morphological filters11,
are more suitable for shape analysis than linear
filters12. The morphology theory can be applied
on either binary or grey-scale images. The
thresholding process defines the corresponding
pixel value as “1” when the grey-scale pixel value
is larger or equal to the threshold value; otherwise,
the pixel value is “0”13. The binary image can
be represented by a set of coordinated for those
pixels with value “1”16. Morphology operation
is suited for binary image processing because of
its relative ordering of pixel values not on
numerical value. Morphology techniques explore
an image with a tiny shape or model called a
structuring element is a small binary image. The
structuring element is positioned at every possible
location of the image and tests whether it “hits” or
intersects the neighborhood.
In erosion, every object pixel that is
tetchy a background pixel is tainted into a
background pixel. In dilation, every background
pixel that is tetchy an object pixel is tainted into an
object pixel. Opening is defined as erosion
followed by dilation. Closing is defined as dilation
followed by erosion. Image differencing and hit or
miss operation is used for comparing two images.
Noise filtering is used for removing the unwanted
information in the communication media. In
proposed technique rank order filtering reduces
impulsive noise10.
II. EXSISTING SYSTEM
The paper presents a binary image
processor that consists of the reconfigurable
binary processing module, including
reconfigurable binary compute units, output
control units, input and output control logic units
and peripheral circuits in Fig 1. The
reconfigurable binary compute units are mixed
grained architecture, which has the characteristics
of high flexibility, efficiency and performance. By
using dynamic reconfigurable approach the
performance of the processor is enhanced. The
processor is implemented to perform real time
binary image processing, has the merit of high
speed, simple structure, and wide application
range.
Fig.1. Architecture of the binary image processor
The input signal given is the image and it
is synchronized by using input control logic unit
therefore processing rate is increased. The
configuration register is used for reconfiguration
of the processor. It is the main part of the
processor. The reconfiguration is control by
process control unit. It also controls the output and
input control logic. The processed image data is
written to SDRAM, the process control unit
transmits interrupt requests to interaction of the
processor with external system.
Fig.2. Reconfigurable binary processing module
Each pixel of the image is taken by
binary compute unit that perform every operation
in parallel manner and execute the result in Fig 2.
Mathematical morphological operation filters used
in the existing system are erosion, dilation,
opening, closing, image differencing, hit or miss,
and noise filtering.
Erosion of a binary image A with a
structuring element B is given by G = A?B with
the location (x,y). The erosion is defined by
A? B = {x| (B)x ? A (1)
Erosion of A by B is a set of consisting of
translated B is contained and equal to A in but not
sharing elements with background of A.
Dilation of a binary image A with a
structuring element B is given by G = A?B with
the location (x,y). The dilation is defined by
A? B = {x| (B^
)x? A?Ø}. (2)
Dilation of A by B is the set consisting of reflected
and translated structuring element intersect the
image is null.
Opening of a binary image A by a
structuring element B is given with the location
(x,y).
A? B = A ? B? B (3)
Closing of a binary image A by a
structuring element B is given with the location
(x,y).
A ? B = A? B ? B (4)
Noise filtering of a binary image A by
structuring element B is given by
{(A?B ? B) ?B}?B = (A?B) ?B (5)
Hit or miss of a binary image A by a
matched pair of structuring element {B1,B2} is
given by
A?{B1,B2} = (A ? B1)? (Ac ?B2) (6)
Image differencing is a common
image processing technique used to estimate the
shifted locations of the object. These operations
are loaded in one reconfigurable processor and
executed the output. This is the main advantage of
the existing system. In the proposed processor
included a generic bit-sliced rank order filter
algorithm has the memory-based architecture
features like high degree of regularity and
flexibility while the performance is high and cost
is low.
III. PROPOSED SYSTEM
The developed system concentrates
on VLSI Design of Rank Order Filtering (ROF)
uses a unique defined memory, called Dual-Cell
Random Access Memory (DCRAM) to recognize
threshold decomposition and polarization
operation by means of a maskable memory for
image processing and real time speech application.
Therefore the proposed processor has high
flexibility, high speed and low cost. Data is given
to the DCRAM cell in which it has both data field
and computing field for data read and writes in Fig
3. Data is read in data field and then given to the
level quantizer for data counting, threshold
decomposition and polarization. Threshold
decomposition means according to the rank the
bits are quantized. i.e. the median value the MSB
bit is changed to high value. The result then goes
to the polarization selector for polarization. Then
the result is given to the shift register. Then a
cycle after the result goes to the output register
(OUTR).
Fig 3: Rank order filter architecture
The bit-sliced rank order filter has been
illustrated in the example given below in Fig 4.
Here N=7 i.e., the number of input samples, B=4
i.e., the number of bits, and r=1 i.e. , the 1st order
filter. The first stage the bit counting stage first
calculate the MSB bits total number of 1’s , if the 1
? r then threshold decomposition step sets the Y1 as
1 otherwise 0. Then the polarization step consider
that the input samples having MSB samples 1’s is
LSB the process stops and the output is generated
i.e., 14(11102). The rank order filter architecture is
directly implementing to the binary image
processor to increase the reconfigurability of the
processor. Therefore we can reduce the noise such
as noise in the communication media, salt and
pepper noises, blurring effects etc

Fig 4: The generic bit-sliced ROF algorithm meant
for N=7, B=4, and r=1 as an example.

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0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1 0 0 0
1 1 1 0 1 1 1 0 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
Y1 1 1 1 X
7 0 1 1 1 0 0 0 0 0 0 0 0
5 0 1 0 1 0 0 0 0 0 0 0 0
11 1 0 1 1 1 0 1 1 1 0 1 1
14 1 1 1 0 1 1 1 0 1 1 1 0
2 0 0 1 0 0 0 0 0 0 0 0 0
8 1 0 0 0 1 0 0 0 1 0 0 0
3 0 0 1 1 0 0 0 0 0 0 0 0
Y 1 X X X Y1 1 1 X X
0 0 0 0
0 0 0 0
1 0 0 0
1 1 1 0
0 0 0 0
1 0 0 0
0 0 0 0
Y1 1 1 1 0
4: Threshold
decomposition
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1 0 0 0
1 1 1 0 1 1 1 0 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
Y1 1 1 1 X
4: Threshold
decomposition
5: Polarization 6: Threshold
decomposition
1: Threshold
decomposition
2: Polarization
2: Polarization
3: Threshold
decomposition
3:Threshold
decomposition
7:Polarization

Result Image Result Image Result Image
Result Image
(a) (b) (c) (d)

Result Image

(e) (f) (g) (h)

(i)

Fig 5: Binary image processing results. (a) Input image (b) Erosion (c) Dilation (d) Opening (e) Closing (f) Hit
or miss (g) Noise filtering (h) Image differencing (i) Structuring Element
The Fig 5 shows the binary image
processing results that input image Fig 5a is the
standard image of house and erosion in Fig 5b
shows that removing the spurious bright spot that
is salt noise is removed and in dilation in Fig 5c
shows fill in small spurious holes that is pepper
noise is removed. In Fig 5d shows the opening
operation in which erosion followed by dilation so
it will remove some of the bright pixels from the
edged of the region of bright pixel. In Fig 5e
shows the closing operation in which dilation
followed by erosion so it will enlarge the
boundaries of the bright regions. In Fig 5f shows
the hit or miss
operation is an intersection operation performed
by two erosion operation with two structuring
element is the detection of end points. In Fig 5g
shows the Noise Filtering operation in which it is
the combination of both dilation and erosion
operation in which noise are filtered. This filtering
operation will ignore the noise in the
communication media. In Fig 5h shows the Image
Differencing operation in which image is
compared with the same image to reduce the
noise. Fig 5i shows the structuring element in
which it is a 5×5 matrix.
0 0 1 0 0
0 0 1 0 0
1 1 1 1 1
0 0 1 0 0
0 0 1 0 0
Fig 6: Reconfigurable Binary Processor Operation
The Fig 6 shows the Reconfigurable
binary processor which shows the every operations
like erosion, dilation, opening, closing, hit or miss,
noise filtering, image differencing, rank order
filtering. The processor shows that every single
operation is executed in the same processor
therefore noise can be filtered. Therefore increasing
the reconfigurability of the processor and finding
the frame rate for each operation is illustrated in
table I and table II shows the summary result.
and we can calculate the frame rate that is
Frame rate = bits / second
We can see that more than 200 frames are
implemented by using the given operation.
TABLE II
SUMMARY RESULT
TABLE I
EXECUTION TIMES AND PERFORMANCE
OF OPERATION
The summary result in Table II shows that
image pixels of any size can be implemented in this
processor. Voltage and power consumption is also
reduced by using this processor. More power is reduced
by using the rank order filtering technique.
The Table I shows the execution time and
performance operation of the processor I which
the processor calculate the times in nano seconds
IV. CONCLUSION
In this paper, binary image processor
architecture was proposed to perform real time
IMAGE PIXELS ANY SIZE
MEMORY
102820
kilobytes
IMAGE PROCESSING
BINARY
SPEED GRADE -4
VOLTAGE 1.2
POWER
CONSUMPTION
0.034 W
OPERATION TIME
(NS)
FRAME
RATE (F/S)
DILATION 4.283 233
EROSION 4.283 233
OPENING 4.283 233
CLOSING 4.283 233
HIT AND MISS 4.310 232
NOISE
FILTERING
4.014 249
IMAGE
DIFFERENCING
4.496 222
RANK ORDER
FILTERING
3.692 270
binary image processing using a reconfigurable
processor. Reconfigurable binary image
processing module is mixed grain architecture
with high efficiency and performance and low
cost. This processor has simple structure, high
speed and wide application range such as
identification and authentication, motion
detection, object tracking, object recognition,
computer vision. In the ROF algorithm shows that
the architecture feature has high degree of
flexibility and regularity to increase the
reconfigurability of the processor. The experiment
and synthesis result shows that the processor is
suitable for binary image processing application.

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